8862 Timing Modulator

8862 Timing Demodulator

1. General

8862 Timing Demodulator is designed to generate timing output pulse for a measurement by receiving a message from timing modulator (patternized timing information; basically 10MHz optical signal) followed to predetermined setting information.

8862 extracts standard clock (PLL) from received message (NRZ signal) with voltage controlled signal generator, then re-produce the original output data. CRC identification code-check tests data so as only verified operation mode is allowed. Up to 8 different timing clocks can be set through each different output connector.

8862 is equipped with inhibit input which disable transactions same as a timing modulator, and trigger input which enable operation test locally.

2. Specifications

Timing signal input

Number of input 1

Input signal Optical pulse signal

Input connector FC connector

Input baud rate 20 M baud max

Trigger input

Number of input 1

Input signal TTL pos logic pulse

Input connector CAMAC connector

Input impedance 1 kΩ

Inhibit input

Number of input 1

Input signal TTL neg logic level (Min. setting: 100 micro sec or wider)

Input connector CAMAC connector

Input impedance 2 kΩ

Clock output

Number of output 1

Output signal TTL pos logic pulse

Out put connector CAMAC connector

Frequency divider clock output

Numbers of output 2

Output signal TTL signal

Output connector CAMAC connector

Delayed pulse output

Numbers of output 8

Output signal TTL signal

Output connector CAMAC connector

Signal bus output

Number of input/output 1

Input/output setting can be made by inside jumper pins

Input/Output signal TTL signal

Input/Output connector CAMAC connector

Event signal output

Number of output 1

Output signal TTL signal

Output connector 10 pins ribbon-connector for HIF PCB

LED display

Delayed pulse output: GRN LED x 8

Setting mode: GRN LED x 2

Setup input: GRN LED x 1

Error alarm: RED LED x 1

Message input: GRN LED x 1

Clock input: GRN LED x 1

On operation: GRN LED x 1

Interrupt generated RED LED x 1

Input enable setting: GRN LED x 1

Inhibit input: RED LED x 1

Trigger input: RED LED x 1

Station N: RED LED x 1

Size

CAMAC standard 2 width module

Power

+ 6 V, less than 2 A

3. Software specification

3-1 CAMAC command summary

Function code	Data	Effective bit #
F (0) A (0)	Control register	R1 – R4
F (0) A (1)	Mode register	R1 – R4
F (0) A (2)	Interrupt mask register	R1 – R8
F (0) A (3)	Trigger register	R1 – R8
F (0) A (4)	Interrupt register	R1 – R8
F (0) A (5)	Event register	R1 – R8
F (0) A (6)	1 sec timer trigger-selection-register	R1 – R8
F (0) A (7)	1 sec timer register	R1 – R16
F (0) A (8)	Received message register (lower 16 bit)	R1 – R16
F (0) A (9)	Ditto (higher 16 bit)	R1 – R16

F (1) A (0)	Delayed-time setting register	R1 – R6
F (1) A (1)	Channel 1 frequency-divider register	R1 – R7
F (1) A (2)	Channel 1 frequency-divider-scaling-rate register	R1 – R4
F (1) A (3)	Channel 2 frequency-divider register	R1 – R7
F (1) A (4)	Channel 2 frequency-divider-scaling-rate register	R1 – R4
F (1) A (5)	Interrupt signal status register	R1 – R8
F (1) A (6)	Delayed-output target-channel setting register	R1 – R3
F (1) A (7)	Delayed-output delay-time setting register (lower 16 bit)	R1 – R16
F (1) A (8)	Delayed-output delay-time setting register (higher 16 bit)	R1 – R16
F (1) A (9)	Delayed-output pulse-width register (lower 16 bit)	R1 – R16
F (1) A (10)	Delayed-output pulse-width register (higher 16 bit)	R1 – R16
F (1) A (11)	Delayed-output repetition-time register	R1 – R16
F (1) A (12)	Delayed-output repetition-time register	R1 – R16
F (1) A (13)	Delayed-output repetition-number register	R1 – R16
F (1) A (14)	Delayed-output trigger-selection register	R1 – R8

Function code	Data	Effective bit #
F (16) A (0)	Control register	W1 – W4
F (16) A (1)	Mode register	W1 – W4
F (16) A (2)	Interrupt mask register	W1 – W8
F (16) A (3)	Trigger register	- - - -
F (16) A (4)	Not used
F (16) A (5)	Not used
F (16) A (6)	1 sec timer trigger-selection-register	W1 – W8
F (16) A (7)	1 sec timer register	- - - -
F (16) A (8)	Not used
F (16) A (9)	Not used

F (20) A (0)	Manual-trigger execution register	W1 – W8
F (20) A (1)	Event execution register	W1 – W8
F (20) A (2)	Manual-inhibit execution register	- - - -
F (20) A (3)	Manual-Un-inhibit execution register	- - - -
F (20) A (4)	Manual-setup execution register	- - - -
F (20) A (5)	Manual-stop execution register	- - - -
F (20) A (6)	Forced-reset execution register	- - - -
		W1 – W6
F (17) A (0)	Delay-time setting register	W1 – W7
F (17) A (1)	Channel 1 frequency-divider register	W1 – W4
F (17) A (2)	Channel 1 frequency-divider-scaling-rate register	W1 – W7
F (17) A (3)	Channel 2 frequency-divider register	W1 – W4
F (17) A (4)	Channel 2 frequency-divider-scaling-rate register
F (17) A (5)	Not used	W1 – W3
F (17) A (6)	Delayed-output target-channel setting register	W1 – W16
F (17) A (7)	Delayed-output delay-time register (lower 16 bit)	W1 – W16
F (17) A (8)	Delayed-output delay-time register (higher 16 bit)	W1 – W16
F (17) A (9)	Delayed-output pulse-width register (lower 16 bit)	W1 – W16
F (17) A (10)	Delayed-output pulse-width register (upper 16 bit)	W1 – W16
F (17) A (11)	Delayed-output repetition-time register (lower 16 bit)	W1 – W16
F (17) A (12)	Delayed-output repetition-time register (upper 16 bit)	W1 – W16
F (17) A (13)	Delayed-output repetition-number register	W1 – W16
F (17) A (14)	Delayed-output trigger-selection register	W1 – W8

Function code	Data	Effective bit #
F (8) A (0)	Test LAM (Test Look at Me)	- - - -
F (9) A (0)	Module clear (clear all register and counter)	- - - -
F (10) A (0)	Clear LAM (Clear Look at Me)	- - - -
F (24) A (0)	Disable LAM	- - - -
F (26) A (0)	Enable LAM	- - - -
F (27) A (0)	NG Test LAM	- - - -

All above function codes, except F (8), and F (27): Return X and Q

* F (8): Return Q when LAM is enabled at Enable-LAM

* F (27): Return Q when LAM is enabled

Initialize (Same action as POWER ON): Z, C

3-2 Interrupt function

By interrupt Look at Me (LAM)

3-3 Interrupt factors: Following factors generate interrupt.

Trigger input: When trigger is activated by message or trigger-input.

Event input: When event message is sent.

Un-inhibit input: When inhibit is disabled (un-inhibit status) by message or inhibit-input.

Inhibit input: When inhibit is enabled by message or inhibit-input.

Error detection: When error is detected in a message sent from modulator.

Clock input: When no clock is detected in optical-signal or clock-frequency is lower than the limit.

Setup input: When message inputs setup-signal.

Stop input: When message inputs stop-signal.

4. Register setting method

4-1 Control register

CAMAC Function Code: F (16) A (0)

This is a basic register, therefore is to be set prior to start operation.

W1 sets event output, enabled “1” or disabled “0”.

W2 sets internal clock, 1MHz “0” or 100KHz “1”.

W3 sets hardware input (trigger), enabled “1” or disabled “0”.

W4 sets clock source, external (optical signal) “0” or internal “1”.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

CAMAC Function Code: F (0) A (0)

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

R1 enables “1” or disables “0” event output function.

R2 sets internal clock, 1MHz “0” or 100KHz “1”.

R3 sets hardware input (trigger), enabled “1” or disabled “0”.

R4 sets clock source, external (optical signal) “0” or internal “1”.

4-2 Mode register

CAMAC Function Code: F (16) A (1)

This is a basic register, therefore is to be set prior to start operation

W1, W2, W3, and W4 are corresponded to Mode0, Mode1, Mode2, and Mode3 respectively. One of four bits is to be set 1

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

CAMAC Function Code: F (0) A (1)

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

R1: Mode0, R2: Mode1, R3: Mode2, R4: Mode3

4-3 Interrupt mask register

CAMAC Function Code: F (16) A (2)

This is a basic register, therefore is to be set prior to start operation.

To enable inhibit, sets corresponding bit to “0”

Initial status is all disabled “1”.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

Enabled is “0” and disabled is “1”

W1: Trigger-input interrupt enabled/disabled

W2: Event-input interrupt enabled/disabled

W3: Un-inhibit-input interrupt enabled/disabled

W4: Inhibit-input interrupt enabled/disabled

W5: Error-alarm interrupt enabled/disabled

W6: No-clock interrupt enabled/disabled

W7: Setup-input interrupt enabled/disabled

W8: Stop-input interrupt enabled/disabled

CAMAC Function Code: F (0) A (2)

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

Enabled is “0” and disabled is “1”

R1: Trigger-input interrupt enabled/disabled

R2: Event-input interrupt enabled/disabled

R3: Un-inhibit-input interrupt enabled/disabled

R4: Inhibit input interrupt enabled/disabled

R5: Error-alarm interrupt enabled/disabled

R6: No-clock interrupt enabled/disabled

R7: Setup-input interrupt enabled/disabled

R8: Stop-input interrupt enabled/disabled

4-4 Trigger register

CAMAC Function Code: F (16) A (3)

When trigger input is issued by message, interrupt will be generated (when enabled). Readout of this register tells which channel is activated. Writing arbitrary number clears the register.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	***	***	***

CAMAC Function Code: F (0) A (3)

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1”: Under following conditions

R1: When channel 1 is activated

R2: When channel 2 is activated

R3: When channel 3 is activated

R4: When channel 4 is activated

R5: When channel 5 is activated

R6: When channel 6 is activated

R7: When channel 7 is activated

R8: When channel 8 is activated

4-5 Interrupt register

CAMAC Function: F (0) A (4)

Readout of this register tells what is the element of interrupt

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1”: When interrupt generated

R1: Trigger-message-input interrupt

R2: Event-message-input interrupt

R3: Un-inhibit-message-input interrupt

R4: Inhibit-message-input interrupt

R5: Clock-error-alarm interrupt

R6: Setup-message-input interrupt

R7: Stop-message-input interrupt

R8: Stop-message-input interrupt

4-6 Event register

CAMAC Function Code: F (0) A (5)

Readout of this register tells what is the content of event message

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

4-7 1 sec timer trigger-selection register

CAMAC Function Code: F (16) A (6)

Trigger-channel-setting (to start 1 sec timer) register

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1”: When selected.

W1: Channel 1

W2: Channel 2

W3: Channel 3

W4: Channel 4

W5: Channel 5

W6: Channel 6

W7: Channel 7

W8: Channel 8

CAMAC Function Code: F (0) A (6)

Readout of this register tells what is the selected channel

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1”: When selected.

R1: Channel 1

R2: Channel 2

R3: Channel 3

R4: Channel 4

R5: Channel 5

R6: Channel 6

R7: Channel 7

R8: Channel 8

4-8 1 sec timer register

CAMAC Function Code: F (16) A (7)

Writing arbitrary number clears register and stops elapsed timer counter

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	***	***	***	***	***	***	***	***

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	***	***	***

CAMAC Function Code: F (0) A (7)

Elapsed time (starts when input is activated to the trigger channel described above) in one sec unit. Readout clears the register and restarts.

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

4-9 Received message register

CAMAC Function Code: F (0) A (8)

Received 16 bits message tells lower 16 bit data

Lower word: R1 – R8 are synchronized codes (8 bits binary)

This code has the same value as 8 bits dipswitch’ set value

Transmitter modulator, receiver modulator, and relay-tranmitting modulator use the same code setting.

R9 and R10 are 2 bits binary that represent modes as follows.

Mode0: 0b00

Mode1: 0b01

Mode2: 0b10

Mode3: 0b11

R11 – R16 are 6 bits binary that represent trigger channel (manual trigger as well) as follows.

Channel 1: 0b000000

Channel 2: 0b000001

Channel 3: 0b000010

Channel 4: 0b000011

Channel 5: 0b000100

Channel 6: 0b000101

Channel 7: 0b000110

Channel 8: 0b000111

Then, when un-inhibit received: 0b010000

When inhibit received: 0b100000

When event-pattern, stop-message, setup-message, or phase-reset-message received:

0b110000

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	TG 5	TG 4	TG 3	TG 2	TG 1	TG 0	M 1	M 0

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	ID 7	ID 6	ID 5	ID 4	ID 3	ID 2	ID 1	ID 0

CAMAC Function Code: F (0) A (9)

Higher word (R1 – R8) is event type (8 bits, bit pattern)

Followings are exceptional special codes

Stop message: 0b11110000

Setup message: 0b00001111

Phase reset message: 0b11111111

R9 – R16: CRC-check-code (8 bits binary)

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	CR 7	CR 6	CR 5	CR 4	CR 3	CR 2	CR 1	CR 0

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	EV 7	EV 6	EV 5	EV 4	EV3	EV 2	EV 1	EV 0

4-10 Manual-trigger execution register

CAMAC Function Code: F (20) A (0)

Writing trigger pattern (bit pattern) operates same as receiving trigger message.

Execution starts when writing completed.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

W1 represents Channel 1 W5 represents Channel 5

W2 represents Channel 2 W6 represents Channel 6

W3 represents Channel 3 W7 represents Channel 7

W4 represents Channel 4 W8 represents Channel 8

4-11 Event execution register

CAMAC Function Code: F (20) A (1)

Writing arbitrary-pattern operates same as receiving event message

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

4-12 Manual-inhibit execution register

CAMAC Function Code: F (20) A (2)

Writing arbitrary number to W1 – W8 executes manual-inhibit operation

This operation is same as receiving inhibit message.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	***	***	***

4-13 Manual-un-inhibit execution register

CAMAC Function Code: F (20) A (3)

Writing arbitrary number to W1 – W8 executes manual-un-inhibit operation

This operation is same as receiving un-inhibit message.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	***	***	***

4-14 Manual-setup execution register

CAMAC Function Code: F (20) A (4)

Writing arbitrary number to W1 – W8 executes manual-setup operation

This operation is same as receiving setup message.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	***	***	***

4-15 Manual-stop execution register

CAMAC Function Code: F (20) A (5)

Writing arbitrary number to W1 – W8 executes manual-stop operation

This operation is same as receiving stop message.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	***	***	***

4-16 Manual-forced-reset execution register

CAMAC Function Code: F (20) A (6)

Writing arbitrary number to W1 – W8 executes manual-forced-reset operation

This operation will not clear register value, although stop each operation.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	***	***	***

4-17 Delay-time setting register

CAMAC Function Code: F (17) A (0)

Writing corresponding number to W1 – W8 sets delay-time

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	1/0	1/0	1/0	1/0	1/0	1/0

W1 – W3 sets 0 – 35 nano sec setting in 5 nano sec increments

W4 – W6 sets 0 – 350 nano sec setting in 50 nano sec increments

Corresponding hard delay-lines are cascading connection type, therefore provide 0 – 35, 50 – 85, 100 – 135, ------, 350 – 385 nano sec setting.

CAMAC Function Code: F (1) A (0)

Readout of R1 – R6 tells set value

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	***	1/0	1/0	1/0	1/0	1/0	1/0

4-18 Channel 1 frequency-divider-scaling-range setting register

CAMAC Function Code: F (17) A (1)

Writing corresponding setting to R1 – R6 sets channel 1 frequency-divider-scaling-range

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1” corresponds

W1: 0.1 micro sec

W2: 1 micro sec

W3: 10 micro sec

W4: 100 micro sec

W5: 1 milli sec

W6: 10 milli sec

W7: 100 milli sec

CAMAC Function Code: F (1) A (1)

Readout of R1 – R7 tells set value in bit pattern

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1” corresponds

R1: 0.1 micro sec

R2: 1 micro sec

R3: 10 micro sec

R4: 100 micro sec

R5: 1 milli sec

R6: 10 milli sec

R7: 100 milli sec

CAMAC Function Code: F (1) A (1)

Readout of R1 – R7 tells set value in bit pattern

4-19 Channel 1 frequency-divider-scaling-rate setting register

CAMAC Code Function: F (17) A (2)

Writing corresponding setting to W1 – W6 sets channel 1 frequency-divider-scaling-rate

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

Following chart shows a code setting for each frequency-divider-scaling-rate.

W4	W3	W2	W1	Scale	W4	W3	W2	W1	Scale
0	0	0	1	1	0	1	1	0	6
0	0	1	0	2	0	1	1	1	7
0	0	1	1	3	1	0	0	0	8
0	1	0	0	4	1	0	0	1	9
0	1	0	1	5

Actual divider output signal frequency (f): f=1/(a*b) where “a” is a set value per section 4-18, and “b” is a set value per section 4-19. When a=1 micro sec, b=5: f=200 KHz

CAMAC Code Function: F (1) A (2)

Readout of R1 – R4 shows set value.

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

Following chart shows a code setting for each scaling rate.

R4	R3	R2	R1	Scale	R4	R3	R2	R1	Scale
0	0	0	1	1	0	1	1	0	6
0	0	1	0	2	0	1	1	1	7
0	0	1	1	3	1	0	0	0	8
0	1	0	0	4	1	0	0	1	9
0	1	0	1	5

4-20 Channel 2 frequency-divider-scaling-range setting register

CAMAC Function Code: F (17) A (3)

Writing corresponding-setting to R1 – R6 sets channel 2 frequency-divider-scaling-range

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1” corresponds

W1: 0.1 micro sec

W2: 1 micro sec

W3: 10 micro sec

W4: 100 micro sec

W5: 1 milli sec

W6: 10 milli sec

W7: 100 milli sec

CAMAC Function Code: F (1) A (3)

Readout of R1 – R7 tells set value in bit pattern

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1” corresponds

R1: 0.1 micro sec

R2: 1 micro sec

R3: 10 micro sec

R4: 100 micro sec

R5: 1 milli sec

R6: 10 milli sec

R7: 100 milli sec

4-21 Channel 2 frequency-divider-scaling-rate setting register

CAMAC Code Function: F (17) A (4)

Writing corresponding-setting to W1 – W6 sets channel 1 frequency-divider-scaling-rate

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

Following chart shows a code setting for each frequency-divider-scaling-rate.

W4	W3	W2	W1	Scale	W4	W3	W2	W1	Scale
0	0	0	1	1	0	1	1	0	6
0	0	1	0	2	0	1	1	1	7
0	0	1	1	3	1	0	0	0	8
0	1	0	0	4	1	0	0	1	9
0	1	0	1	5

Actual divider output signal frequency is calculated same as channel 1

CAMAC Code Function: F (1) A (4)

Readout of R1 – R4 shows set value.

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	***	***	***	1/0	1/0	1/0	1/0

Following chart shows a code setting for each divider-scaling-rate.

R4	R3	R2	R1	Scale	R4	R3	R2	R1	Scale
0	0	0	1	1	0	1	1	0	6
0	0	1	0	2	0	1	1	1	7
0	0	1	1	3	1	0	0	0	8
0	1	0	0	4	1	0	0	1	9
0	1	0	1	5

4-22 Interrupt signal status readout register

CAMAC Function Code: F (1) A (5)

Readout of R1 – R8 data allows reading interrupt-signal input-status without getting interference from interrupt-mask.

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1” corresponds transaction level

R1: Trigger message input interrupt

R2: Event message input interrupt

R3: Un-inhibit message input interrupt

R4: Inhibit message input interrupt

R5: Clock error alarm interrupt

R6: Setup message input interrupt

R7: Stop message input interrupt

4-23 Delayed-pulse-output target-channel setting register

CAMAC Function Code: F (17) A (6)

Writing corresponding value to W1 – W3 sets desired delayed- pulse-output target-channel.

This setting is to be made prior to following sections setting (4-24, 4-25, and 4-27).

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	***	***	***	***	***	1/0	1/0	1/0

Following chart shows a code setting for each scaling rate.

W3	W2	W1	Selected Channel	W3	W2	W1	Selected Channel
0	0	0	1	1	0	1	6
0	0	1	2	1	1	0	7
0	1	0	3	1	1	1	8
0	1	1	4
1	0	0	5

CAMAC Function Code: F (1) A (6)

Readout of R1 – R3 represent set value.

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	***	***	***	***	***	1/0	1/0	1/0

Following chart shows a code setting for each scaling rate.

R3	R2	R1	Selected Channel	R3	R2	R1	Selected Channel
0	0	0	1	1	0	1	6
0	0	1	2	1	1	0	7
0	1	0	3	1	1	1	8
0	1	1	4
1	0	0	5

4-24 Delay-time setting register

Writing 32 bits (binary pattern) value allows to set delay-time in 1 micro sec increment.

Lower word W1 – W16 represents lower 4 digit and higher word W1 – W16 represents higher 4 digit setting.

Lower word CAMAC Function Code: F (17) A (7)

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word CAMAC Function Code: F (17) A (8)

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

Each word register data readout represents set value.

Lower word CAMAC Function Code: F (1) A (7)

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word CAMAC Function Code: F (1) A (8)

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

4-25 Pulse-width setting register

Writing 32 bits (binary pattern) value allows to set pulse-width in 1 micro sec increment.

Lower word W1 – W16 and higher word W1 – W16 needed to be set

Lower word CAMAC Function Code: F (17) A (9)

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word CAMAC Function Code: F (17) A (10)

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

Each word register data readout represents set value.

Lower word CAMAC Function Code: F (1) A (9)

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word CAMAC Function Code: F (1) A (10)

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

4-26 Repetition-time setting register

Writing 32 bits (binary pattern) value allows to set repetition-time in increment of 1 micro sec.

Lower word W1 – W16 and higher word W1 – W16 needed to be set

Lower word CAMAC Function Code: F (17) A (11)

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word CAMAC Function Code: F (17) A (12)

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

Each word register data readout represents set value.

Lower word CAMAC Function Code: F (1) A (11)

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word CAMAC Function Code: F (1) A (12)

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

4-27 Repetition-number setting register

CAMAC Function Code: F (17) A (13)

Writing value (binary pattern) to W1 – W16 allows to set repetition-number.

Bit	W16	W15	W14	W13	W12	W11	W10	W9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

CAMAC Function Code: F (1) A (13)

Each word register data readout represents set value.

Bit	R16	R15	R14	R13	R12	R11	R10	R9
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

4-28 Trigger-channel setting register (8 bits)

CAMAC Function Code: F (17) A (14)

This register sets trigger channel (bit pattern) that starts delayed pulse counting.

Bit	W8	W7	W6	W5	W4	W3	W2	W1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

Bit and trigger channel correspondences (when selected: “1”

W1: Channel 1

W2: Channel 2

W3: Channel 3

W4: Channel 4

W5: Channel 5

W6: Channel 6

W7: Channel 7

W8: Channel 8

CAMAC Function Code: F (1) A (14)

R1 – R8 register data readout shows set trigger channel number.

Bit	R8	R7	R6	R5	R4	R3	R2	R1
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

Bit and trigger channel correspondences (when selected: “1”)

R1: Channel 1

R2: Channel 2

R3: Channel 3

R4: Channel 4

R5: Channel 5

R6: Channel 6

R7: Channel 7

R8: Channel 8

5. Basic operation setting

Please set execution sequence, by setting-register, waiting-signal, and analyzing-interrupt-factors according to the following flow chart.

Readout of received message, etc.

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