8862 Timing Modulator

8736 Timing Demodulator

1. General

8736 Timing Demodulator is designed to generate timing output pulse for a measurement by receiving a message from timing modulator (patternized timing information; basically 10MHz optical signal) followed to predetermined setting information.

8736 extracts standard clock (PLL) from received message (NRZ signal) with voltage controlled signal generator, then re-produce the original output data. CRC identification code-check tests data so as only verified operation mode is allowed. Up to 8 different timing clocks can be set through each different output connector.

8736 is equipped with inhibit input which disable transactions same as a timing modulator, and trigger input which enable operation test locally.

2. Hardware specifications

Timing signal input

Number of input 1

Input signal Optical pulse signal

Input connector FC connector

Input baud rate 20 M baud max

Trigger input

Number of input 1

Input signal TTL pos logic pulse

Input connector CAMAC connector

Input impedance 1 kΩ

Inhibit input

Number of input 1

Input signal TTL neg logic pulse

Input connector CAMAC connector

Input impedance 2

Clock output

Number of output 1

Output signal TTL pos logic pulse

Out put connector CAMAC connector

Frequency divider clock output

Numbers of output 2

Output signal TTL signal

Output connector CAMAC connector

Delayed pulse output

Numbers of output 8

Output signal TTL signal

Output connector CAMAC connector

Signal bus output

Number of input/output 1

Input/output setting can be made by inside jumper pins

Input/Output signal TTL signal

Input/Output connector CAMAC connector

Event signal output

Number of output 1

Output signal TTL signal

Output connector 10 pins ribbon-connector for HIF PCB

LED display

Delayed pulse output: GRN LED x 8

Setting mode: GRN LED x 2

Error alarm: RED LED x 1

Message input: GRN LED x 1

Clock input: GRN LED x 1

On operation: GRN LED x 2

Interrupt generated RED LED x 1

Input enable setting: GRN LED x 1

Inhibit input: RED LED x 1

Trigger input: RED LED x 1

Size

VME standard 2 width module

Power

+ 6 V, less than 2 A

3. Software specification

3-1 Allowed setting address: 0xC0000 – 0xCFFFF

A8 – A15: By 8 bits dipswitches

Possible base address, by these switches (BASE_ADD)

0xC0000

0xC0100

0xC0200

0xCFE00

0xCFF00

A1 – A7 are listed in a following table

As a function is pre-fixed (express as FIX_ADD), actual address (ADD) can be expressed as follows.

ADD = BASE_ADD + FIX_A

Fixed address	Higher bytes	Lower bytes	Access
0x00	Not used	Control register	R/W
0x02	Not used	Mode register	R/W
0x04	Not used	Interrupt mask register	R/W
0x06	Not used	Trigger register	R/W
0x08	Not used	Interrupt register	R/W
0x0A	Not used	Event register	R
0x0C	Not used	1 sec timer trigger-selection register	R/W
0x0E	1 sec timer trigger register		R/W
0x10	Received message register (lower 16 bits)		R
0x12	Received message register (higher 16 bits)		R
0x14	Not used	Manual-trigger execution register	W
0x16	Not used	Event execution register	W
0x18	Not used	Manual-inhibit execution register	W
0x1A	Not used	Manual-un-inhibit execution register	W
0x1C	Not used	Manual-setup execution register	W
0x1E	Not used	Manual-stop execution register	W

Fixed address	Higher bytes	Lower bytes	Access
0x20	Not used	Forced-reset execution register	W
0x22	Not used	Delay-time setting register	R/W
0x24	Not used	Channel 1 frequency-divider register	R/W
0x26	Not used	Channel 1 frequency-divider-scaling-rate register	R/W
0x28	Not used	Channel 2 frequency-divider register	R/W
0x2A	Not used	Channel 2 frequency-divider-scaling-rate register	R/W
0x2C	Not used	Not used	R/W
0x2E	Not used	Delayed-output target-channel setting register	W
0x30	Delayed output – Delay-time register (lower 16 bits)		R/W
0x32	Delayed output – Delay-time register (higher 16 bits)		R/W
0x34	Delayed output – Pulse-width register (lower 16 bits)		R/W
0x36	Delayed output – Pulse-width register (higher 16 bits)		R/W
0x38	Delayed output – Repetition-time register (lower 16 bits)		R/W
0x3A	Delayed output – Repetition-time register (higher 16 bits)		R/W
0x3B	Delayed output – Repetition-number register		R/W
0x3E	Not used	Delayed-output – Trigger selection register	R/W

3-2 Interrupt function

Select one function from IRQ1 – IRQ7 by jumper connection

Interrupt vector: Set by 8 bits dipswitch

3-3 Interrupt factors: Following factors generate interrupts.

Trigger input: When trigger is activated by message or trigger-input.

Event input: When event message is sent.

Un-inhibit input: When inhibit is disabled (un-inhibit status) by message or inhibit-input.

Inhibit input: When inhibit is enabled by message or inhibit-input.

Error detection: When error is detected in a message sent from modulator.

Clock input: When no clock is detected in optical-signal or clock-frequency is lower than the limit.

Setup input: When message inputs setup-signal.

Stop input: When message inputs stop-signal.

4. Register setting method

4-1 Control register (8bits)

This is a basic register, therefore is to be set prior to start operation.

D0 sets event output, enabled “1” or disabled “0”.

D1 sets VME bus interrupt, enabled “1” or disabled ”0”

D2 sets internal clock, 1MHz “0” or 100KHz “1”.

D3 sets hardware input (trigger), enabled “1” or disabled “0”.

D4 sets clock source, external (optical signal) “0” or internal “1”.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	1/0	1/0	1/0	1/0	1/0

4-2 Mode register (8 bits)

This is a basic register, therefore is to be set prior to start operation.

D0, D1, D2, and D3 correspond to Mode0, Mode1, Mode2, and Mode3, respectively.

One of the above bits is to be set “1”

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	1/0	1/0	1/0	1/0

4-3 Interrupt mask register (8 bits)

This is a basic register, therefore is to be set prior to start operation.

Set interrupt-enabling-target-bit status to “0”.

Initial status is all disabled “1”

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“0” enable followings

D0: Trigger input interrupt

D1: Event input interrupts

D2: Un-inhibit input interrupt

D3: Inhibit input interrupt

D4: Error alarm interrupt

D5: No clock interrupt

D6: Setup input interrupt

D7: Stop input interrupt

4-4 Trigger register (8 bits)

When a trigger input is issued by a message, interrupt will be generated (when enabled).

Readout of this register tells a channel number. Writing an arbitrary number clears the register.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1”: Under following conditions

D0: When channel 1 is activated

D1: When channel 2 is activated

D2: When channel 3 is activated

D3: When channel 4 is activated

D4: When channel 5 is activated

D5: When channel 6 is activated

D6: When channel 7 is activated

D7: When channel 8 is activated

4-5 Interrupt register (8 bits)

Readout of this register tells what is the element of interrupt

Readout clears the register, then interrupt will be terminated.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1”: When interrupt generated

D0: Trigger-message-input interrupt

D1: Event-message-input interrupt

D2: Un-inhibit-message-input interrupt

D3: Inhibit-message-input interrupt

D4: Error-alarm interrupt

D5: Clock-error-alarm interrupt

D6: Setup-message-input interrupt

D7: Stop-message-input interrupt

4-6 Event register (8 bits)

Readout of this register tells what is the content of event message

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

4-7 1 sec timer trigger selection register (8 bits)

1 sec timer start-channel-setting register

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1”: When selected.

D0: Channel 1 D4: Channel 5

D1: Channel 2 D5: Channel 6

D2: Channel 3 D6: Channel 7

D3: Channel 4 D7: Channel 8

4-8 1 sec timer register (16 bits)

Elapsed time (starts when input activated to the trigger channel described above) in one sec unit. Writing an arbitrary number clears the register and stops elapsed timer counter

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

4-9 Received message register (32 bits)

Received 32 bits message can be readout.

Lower word: D0 – D7 are synchronized codes (8 bits binary)

This code has the same value as 8 bits dipswitch’ set value

Transmitter modulator, receiver modulator, and relay-transmitter modulator use the same code setting.

D8 and D9 are 2 bits binary that represent modes as follows.

Mode 0: 0b00

Mode 1: 0b01

Mode 2: 0b10

Mode 3: 0b11

D10 – D15 are 6 bits binary that represent trigger channel (manual trigger as well).

Channel 1: 0b000000 Channel 5: 0b000100

Channel 2: 0b000001 Channel 6: 0b000101

Channel 3: 0b000010 Channel 7: 0b000110

Channel 4: 0b000011 Channel 8: 0b000111

Then, when un-inhibit received: 0b010000

When inhibit received: 0b100000

When event-pattern, stop-message, setup-message, or phase-reset-message received:

0b110000

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	TG 5	TG 4	TG 3	TG 2	TG 1	TG 0	M 1	M 0

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	ID 7	ID 6	ID 5	ID 4	ID 3	ID 2	ID 1	ID 0

Higher word (D0 – D7) is event type (8 bits, bit pattern)

Followings are exceptional special codes

Stop message: 0b11110000

Setup message: 0b00001111

Phase reset message: 0b11111111

D8 – D15: CRC-check-code (8 bits binary)

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	CR 7	CR 6	CR 5	CR 4	CR 3	CR 2	CR 1	CR 0

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	EV 7	EV 6	EV 5	EV 4	EV3	EV 2	EV 1	EV 0

4-10 Manual-trigger execution register (8 bits)

Writing 8 bits trigger pattern (bit pattern) operates same as a received trigger message.

Execution starts when writing completed.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

D0 represents Channel 1 D4 represents Channel 5

D1 represents Channel 2 D5 represents Channel 6

D2 represents Channel 3 D6 represents Channel 7

D3 represents Channel 4 D7 represents Channel 8

4-11 Event execution register (8 bits)

Writing 8 bits arbitrary-pattern operates same as receiving event message

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	***	***	***	***

4-12 Manual-inhibit execution register (8 bits)

Writing 8 bits arbitrary number executes manual-inhibit operation

This operation is same as receiving inhibit message.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	***	***	***	***

4-13 Manual-un-inhibit execution register (8 bits)

Writing arbitrary 8 bits number executes manual-un-inhibit operation

This operation is same as receiving un-inhibit message.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	***	***	***	***

4-14 Manual-setup execution register (8 bits)

Writing arbitrary 8 bits number executes manual-setup operation

This operation is same as receiving setup message.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	***	***	***	***

4-15 Manual-stop execution register (8 bits)

Writing arbitrary 8 bits number executes manual stop operation

This operation is same as receiving stop message.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	***	***	***	***

4-16 Manual-forced-reset execution register (8 bits)

Writing arbitrary 8 bits number executes a manual-forced-reset operation

This operation will not clear register value, although stop each operation.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	***	***	***	***

4-17 Delay-time setting register (8bits)

Writing corresponding 8 bits number sets delay-time

Readout of register data represents setting value

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	1/0	1/0	1/0	1/0	1/0	1/0

D0 – D2 sets 0 – 35 nano sec setting in 5 nano sec increments

D3 – D5 sets 0 – 350 nano sec setting in 50 nano sec increments

Corresponding hard delay-lines are cascading connection type, therefore provide 0 – 35, 50 – 85, 100 – 135, ------, 350 – 385 nano sec setting.

Fixed offset delay time is appx. 10 nano sec

4-18 Channel 1 frequency-divider-scaling-range setting register (8bits)

Writing corresponding 8 bits value sets channel 1 frequency-divider-scaling-range

Readout of register data represents setting value

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1” corresponds

D0: 0.1 micro sec D4: 1 milli sec

D1: 1 micro sec D5: 10 milli sec

D2: 10 micro sec D6: 100 milli sec

D3: 100 micro sec

4-19 Channel 1 frequency-divider-scaling-rate setting register (8 bits)

Writing corresponding 8 bits value sets channel 1 frequency-divider-scaling-rate

Readout of register data represents setting value

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	1/0	1/0	1/0	1/0

Following chart shows a code setting for each frequency-divider-scaling-rate.

D3	D2	D1	D0	Scale	D3	D2	D1	D0	Scale
0	0	0	1	1	0	1	1	0	6
0	0	1	0	2	0	1	1	1	7
0	0	1	1	3	1	0	0	0	8
0	1	0	0	4	1	0	0	1	9
0	1	0	1	5

Actual divider output signal frequency (f): f=1/(a*b) where “a” is a set value per section 4-18, and “b” is a set value per section 4-19. When a=1 micro sec, b=5: f=200 KHz

4-20 Channel 2 frequency-divider-scaling-range setting register (8 bits)

Writing corresponding-setting to R1 – R6 sets channel 2 frequency-divider-scaling-range

Readout of register data represents setting value

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	1/0	1/0	1/0	1/0	1/0	1/0	1/0

“1” corresponds

D0: 0.1 micro sec

D1: 1 micro sec

D2: 10 micro sec

D3: 100 micro sec

D4: 1 milli sec

D5: 10 milli sec

D6: 100 milli sec

4-21 Channel 2 frequency-divider-scaling-rate setting register (8bits)

Writing corresponding 8 bits value sets channel 1 frequency-divider-scaling-rate

Readout of register data represents setting value

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	1/0	1/0	1/0	1/0

Following chart shows a code setting for each divider-scaling-rate.

D3	D2	D1	D0	Scale	D3	D2	D1	D0	Scale
0	0	0	1	1	0	1	1	0	6
0	0	1	0	2	0	1	1	1	7
0	0	1	1	3	1	0	0	0	8
0	1	0	0	4	1	0	0	1	9
0	1	0	1	5

Actual divider output signal frequency is calculated same as channel 1

4-22 Delayed-pulse-output target-channel setting register (8bits)

Writing corresponding 8 bits value sets desired delayed- pulse-output target-channel.

This setting is to be made prior to following sections setting (4-23, 4-24, 4-25 and 4-26).

Readout of the register represents set value.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	***	***	***	***	***	1/0	1/0	1/0

Following chart shows a code setting for each scaling rate.

D2	D1	D0	Selected Channel	D2	D1	D0	Selected Channel
0	0	0	1	1	0	1	6
0	0	1	2	1	1	0	7
0	1	0	3	1	1	1	8
0	1	1	4
1	0	0	5

4-23 Delay-time setting register (32 bits)

Writing 32 bits (binary pattern) value allows to set delay-time in 1 micro sec increment.

Lower word (16 bits) represents lower 4 digit and higher word (16 bits) represents higher 4 digit setting.

Readout of the register represents set value.

Lower word

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

4-24 Pulse-width setting register (32 bits)

Writing 32 bits (binary pattern) value allows to set pulse-width in 1 micro sec increment.

Lower word (16 bits for lower 4 digits) and higher word (16 bits for higher 4 digits) needed to be set. Readout of the register represents set value.

Lower word

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

4-25 Repetition-time setting register (32 bits)

Writing 32 bits (binary pattern) value sets repetition-time in increment of 1 micro sec.

Lower word (16 bits for lower 4 digits) and higher word (16 bits for higher 4 digits) needed to be set. Readout of the register represents set value.

Lower word

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	2⁷	2⁶	2⁵	2⁴	2³	2²	2¹	2⁰

Higher word CAMAC Function Code: F (17) A (12)

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	2³¹	2³⁰	2²⁹	2²⁸	2²⁷	2²⁶	2²⁵	2²⁴

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

4-26 Repetition-number setting register (16 bits)

Writing 16 bits value (binary pattern) sets repetition-number.

Readout of the register represents set value.

Bit	D15	D14	D13	D12	D11	D10	D9	D8
Setting	2¹⁵	2¹⁴	2¹³	2¹²	2¹¹	2¹⁰	2⁹	2⁸

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	2²³	2²²	2²¹	2²⁰	2¹⁹	2¹⁸	2¹⁷	2¹⁶

4-27 Trigger-channel setting register (8 bits)

This register sets trigger channel (bit pattern) that starts delayed pulse counting.

Readout of the register represents set value.

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Setting	1/0	1/0	1/0	1/0	1/0	1/0	1/0	1/0

Bit and trigger channel correspondences (when selected: “1”

D0: Channel 1

D1: Channel 2

D2: Channel 3

D3: Channel 4

D4: Channel 5

D5: Channel 6

D6: Channel 7

D7: Channel 8

5. Basic operation setting

Please set execution sequence, by setting-register, waiting-signal, and analyzing-interrupt-factors according to the following flow chart.

Readout of received message, etc.

Return